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Research and implementation of digital down conversion based on FPGA

0 introduction

restricted by the existing technical level, in the current signal conversion system, most of the RF signal is first converted to the intermediate frequency through one or several analog down conversion, and then the signal is digitized at the intermediate frequency, and then the digital down conversion is carried out. Digital down conversion is one of the core technologies of software radio. With the gradual maturity of broadband wireless communication technologies such as WiMAX, the requirements for digital bandwidth of wireless devices are becoming higher and higher. Therefore, it is necessary to study the digital down conversion of signals with wide bandwidth

l common digital down conversion structure

the common digital down conversion structure is shown in Figure 1. The digital down conversion can be divided into two basic modules: the numerical control oscillator (NCO) mixing module and the decimation filter module. The NCO module generates sine and cosine wave sample values, and then multiplies them with the input data to complete mixing

the common structure of decimation filter module is the cascade of integral comb decimation filter (CIC) and multi-stage half band filter (HBF). If the signal bandwidth is wide and the decimation multiple is not large, FIR filter can be used. When the sampling rate of the input signal is very high, the down conversion scheme of polyphase filtering can be adopted, and the operation link is arranged after extraction. This structure greatly reduces the requirements for data processing speed

2 design of signal down conversion scheme

set the IF frequency of the signal as the typical value of 70 MHz, and the bandwidth as lo MHz, then the baseband bandwidth B is 5 MHz. According to Nyquist sampling theorem, the sampling frequency of this signal cannot be lower than 2B, that is, 10 MHz, and generally greater than 2.5B, that is, 12.5 MHz in practical application. At present, commercial digital down converter chips are designed based on CIC and HbF cascading mode. When the sampling rate is large and the extraction multiple is small, the chip processing bandwidth is relatively narrow, and the filtering performance of filter banks is not ideal. At the same time, the data processing speed of DSP chip can not meet the requirements, so FPGA is used to realize the digital down conversion system

2.1 determination of sampling frequency FS

because the frequency of oversampling is required to be more than 150 MHz, the rate is relatively high, and it is not easy to realize, so the design scheme adopts band-pass sampling. According to Shannon's bandpass sampling theorem, Let f (T) be a bandpass signal, and its passthrough is (FL, FH). In the case of real signal sampling, its sampling frequency FS should meet the following conditions before f (T) can be recovered from its sampled signal reconstruction:

where: n is a positive integer satisfying the following formula. From the following formula, 1 N 6 can be calculated. When n takes different values, fatigue state can be generated. The value range of each sampling rate is shown in Table 1

the sampling rate is high, and the anti aliasing filter before ADC is relatively easy to implement. At the same time, the ADC signal-to-noise ratio (SNR) formula is as follows:

snr=[6.02b+1.76+101g (FS/2b)]db

where: B is the sampling bits of ADC. It can be seen that the higher the sampling rate, the higher the SNR of ADC. Therefore, the sampling rate should be increased, but at the same time, the operation speed of the later stage should also be considered

2.2 NCO design

there are four main down conversion methods:

(1) look up table method generates sine and cosine wave sample values, and then mixing

(2) IIR oscillator generates digital sine and cosine function and then mixes

(3) coordinate rotation digital computer (CORDIC) algorithm using pipeline technology

(4) resampling

two methods (1) and (3) are used most in practice

method (1) produces the following sine and cosine wave sample values:

s (n) =cos[2 (FC/Fs) n], n=o, 1, 2,

but we hope that the insulation board can play a heat insulation role in summer

where: FC is the local oscillation frequency of NCO, which meets fc=70 FS. These sample values are multiplied by the signal sampling value to complete mixing

using the look-up table method to achieve high accuracy requires a lot of fp-ga ROM resources, while method (3) does not need to consume so much resources. Although the use of pipelining technology will cause the output to produce a delay of iterations and clock cycles, it is a better implementation method to omit two multipliers

further study the sampling rate and let fs=mfc. From the expression of S (n), if M is an integer, the obvious sample value can be simplified from the huge look-up table data to M data. Substituting fs=mfc into fc=70 FS, we can get:

combined with table 1 and the above formula, considering all kinds of situations, take n=2, m=4, fs=56 MHz, then s (n) =cos (n/2), n=o, 1, 2. It can be seen that the sample value of sine and cosine wave is only 1, -1, 0. When mixing, it only keeps the input data unchanged, takes negative and sets 0, omits two multipliers, saves resources to the greatest extent, and avoids the non orthogonal error caused by the truncation of the bits of sine and cosine value

2.3 design of decimation filter

from the above discussion, the sampling rate is determined to be 56 MHz, and the accuracy is 12 B. Four times of the input data is extracted, and the obtained data rate is 14 MHz, which is greater than 12.5 MHz, meeting the requirements

cic filter is suitable for narrow-band high decimation rate, which is not suitable here. Therefore, FIR filter is used as decimation anti aliasing filter, and quadruple decimation is divided into two levels, double decimation, and half band filter is used for both levels of decimation

select linear sys filters of system view to design the filter, and use the equal ripple method to make the design error evenly distributed in the whole frequency band. The parameters of the first half band filter are as follows: sampling rate fs=56 MHz, filter passband cut-off frequency 5 MHz, stopband starting frequency (56/2) -5=23 MHz, transition band bandwidth =18 MHz, stopband attenuation -60 dB, passband ripple coefficient 0.01 dB. Because the stopband starting frequency of the filter is large and the transition band is correspondingly wide, the order of the designed half band filter is only ll order, and the values of the coefficients after 12 b quantization are as follows:

[36, 0, -230, 0, 1217, 2047, 1217, 0, -230, 0, 36]

similarly, the order of the second half band filter is 23 orders, The quantized value of the coefficient is:

[-10, 0, 33, O, -80, 0172, 0, -376, O, 1285, 2047, 1285, 0, -376, 0172, 0, -80, O, 33, 0, -10]

FPGA implementation of the scheme

from the above NCO design, the mixing part is very easy to implement, and the key part is the implementation of the filter

The half band filter produced by the design tool has a symmetrical structure, and only half of its coefficients can be used. Considering the high data input rate of the filter and the saving of FPGA resources, the fully parallel distributed algorithm (DA) filter is adopted, and the filtering operation can be completed once per clock cycletaking the first stage filter as an example, the specific implementation method is as follows:

(1) due to the symmetry of the coefficients, the input data with the same filter coefficients can be added first, and only four of them are used to simplify the structure and save resources. The input data is 12 b, and the bit width is extended by one bit to 13 B after adding

(2) adopting the fully parallel Da structure, each bit of data has a look-up table with a depth of 24. The data is divided into a group every 3 bits, and the last group is 4 bits. The table lookup results of each group are shifted by the corresponding bits and added. The results are input into the two-stage pipeline adder array, and finally the filtered output value is obtained

(3) three problems that should be paid attention to in the design:

① quantization of filter coefficients, expand the coefficients by 2L times, and finally shift the output to the right by L bits

② establishment of lookup table. Since there are only four coefficients, there is no need to group the coefficients and look up the table separately to save lookup table resources

③ the processing of data bits in the operation should not overflow

the implementation of the second stage filter is similar to that of the first stage filter

4 simulation and result analysis

fpga chip adopts Stratix Ⅱ ep2s15f484c3 of Altera company. After layout and wiring in Quartus Ⅱ 7.2, the resource consumption is shown in Table 2

the maximum operating frequency of the circuit is 176.15 MHz, which meets the requirements. Generate a sweep signal with a spectrum bandwidth of 5 MHz, mix the signal with a cosine signal with a frequency of 70 MHz to the intermediate frequency, and import its sampled value into Modelsim 6.0 for simulation. The timing simulation results are shown in Figure 2

in Figure 2, the upper part is the input intermediate frequency signal, and the lower part is the output I-channel signal. It can be seen from the figure that the original swept frequency signal is obtained from channel I, which verifies the correctness of the design

next, consider another down conversion scheme for comparison. If the same signal is sampled at a rate of 60 MHz, the frequency of NCO is 10 MHz, and the period of sine and cosine sample values is 6. Two multipliers are needed for mixing, and the order of the designed filter is also increased. The FPGA resources consumed after layout and wiring exceed the previous design

5 conclusion

from the above discussion, the advantages of choosing an appropriate sampling rate are as follows:

(1) it can reduce the number of sample values of NCO, thereby reducing the resource consumption during mixing

(2) the design of decimation filter can be simplified

at the same time, using the filter based on the parallel Da algorithm, you can add the second nano material (such as carbon nanotubes or silicon carbide) and graphene at the same time, which can have a significant impact on the performance. Aerogel is the use of a wide range of basic strategic cutting-edge new materials to achieve high-speed filtering function with small hardware resources. Based on the above advantages, the digital down conversion scheme designed in this paper completes the digital down conversion of signals with less resources, which has important practical value

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